Bibliography of Publications Related to HOL

[1] M. Aagaard, M. E. Leeser, and P. J. Windley. Toward a super duper hardware tactic. In J. J. Joyce and C.-J. H. Seger, editors, Higher Order Logic Theorem Proving and its Applications: 6th International Workshop, HUG'93, Vancouver, B.C., August 11-13 1993: Proceedings, volume 780 of Lecture Notes in Computer Science, pages 399-412. Springer-Verlag, 1994.
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[2] S. Agerholm. Domain theory in HOL. In J. J. Joyce and C.-J. H. Seger, editors, Higher Order Logic Theorem Proving and its Applications: 6th International Workshop, HUG'93, Vancouver, B.C., August 11-13 1993: Proceedings, volume 780 of Lecture Notes in Computer Science, pages 295-310. Springer-Verlag, 1994.
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[3] S. Agerholm. Formalising a model of the lambda-calculus in HOL-st. Technical Report 354, University of Cambridge Computer Laboratory, 1994.
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[4] S. Agerholm. A HOL basis for reasoning about functional programs. Technical Report BRICS Technical Report RS-94-44, Department of Computer Science, University of Aarhus, December 1994.
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[5] S.Agerholm. LCF examples in HOL. The Computer Journal, 38(2):121-130, July 1995.
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[6] S.Agerholm. LCF examples in HOL. In T. F. Melham and J. Camilleri, editors, Higher Order Logic Theorem Proving and Its Applications: 7th International Workshop, Valletta, Malta, September 1994: Proceedings, volume 859 of Lecture Notes in Computer Science, pages 1-16. Springer-Verlag, 1994.
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[7] S. Agerholm. Mechanizing program verification in HOL. In M. Archer, J. J. Joyce, K. N. Levitt, and P. J. Windley, editors, Proceedings of the 1991 International Workshop on the HOL Theorem Proving System and its Applications, Davis, August 1991, pages 208-222. IEEE Computer Society Press, 1992.
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[8] S.Agerholm. Mechanizing program verification in HOL. Technical Report DAIMI Report Number IR-111, Department of Computer Science, University of Aarhus, April 1992.
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[9] S.Agerholm. Non-primitive recursive function definition. In E. T. Schubert, P. J. Windley, and J. Alves-Foss, editors, Higher Order Logic Theorem Proving and Its Applications: 8th International Workshop, Aspen Grove, Utah, September 1995: Proceedings, volume 971 of Lecture Notes in Computer Science, pages 17-31. Springer-Verlag, 1995.
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[10] S.Agerholm, I. Beylin, and P. Dybjer. A comparison of HOL and ALF formalizations of a categorical coherence theorem. In J. von Wright, J. Grundy, and J. Harrison, editors, Theorem Proving in Higher Order Logics: 9th International Conference, Turku, Finland, August 1996: Proceedings, volume 1125 of Lecture Notes in Computer Science, pages 17-32. Springer-Verlag, 1996.
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[11] S. Agerholm and M. Gordon. Experiments with ZF set theory in HOL and Isabelle. In E. T. Schubert, P. J. Windley, and J. Alves-Foss, editors, Higher Order Logic Theorem Proving and Its Applications: 8th International Workshop, Aspen Grove, Utah, September 1995: Proceedings, volume 971 of Lecture Notes in Computer Science, pages 32-45. Springer-Verlag, 1995.
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[12] S. Agerholm and H. Skjødt. Automating a model checker for recursive modal assertions in HOL. Technical Report DAIMI Report Number IR-92, Department of Computer Science, University of Aarhus, January 1990.
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[13] O. Aït Mohamed. Mechanizing a pi-calculus equivalence in HOL. In E. T. Schubert, P. J. Windley, and J. Alves-Foss, editors, Higher Order Logic Theorem Proving and Its Applications: 8th International Workshop, Aspen Grove, Utah, September 1995: Proceedings, volume 971 of Lecture Notes in Computer Science, pages 1-16. Springer-Verlag, 1995.
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[14] O. Aït Mohamed. The theory of the pi-calcul in HOL. PhD thesis, Henri Poincare University, July 1996.
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[15] J. Alves-Foss, editor. HOL-95: International Workshop on Higher Order Logic Theorem Proving and its Applications: B-Track: Short Presentations, Aspen Grove, Utah, September, 1995, 1995.
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[16] J. Alves-Foss. Modelling non-deterministic systems in HOL. In L. J. M. Claesen and M. J. C. Gordon, editors, Higher Order Logic Theorem Proving and its Applications: Proceedings of the IFIP TC10/WG10.2 International Workshop, Leuven, September 1992, IFIP Transactions A-20, pages 295-304. North-Holland, 1993.
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[17] J. Alves-Foss and K. Levitt. Mechanical verification of secure distributed systems in higher order logic. In M. Archer, J. J. Joyce, K. N. Levitt, and P. J. Windley, editors, Proceedings of the 1991 International Workshop on the HOL Theorem Proving System and its Applications, Davis, August 1991, pages 263-278. IEEE Computer Society Press, 1992.
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[18] J. Alves-Foss and K. Levitt. Verification of secure distributed systems in higher order logic: A modular approach using generic components. In Proceedings of the 1991 IEEE Computer Society Symposium on Research in Security and Privacy; Oakland, California, May 1991, pages 122-135, 1991.
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[19] F. Andersen, U. Binau, K. Nyblad, K. D. Petersen, and J. S. Pettersson. The HOL-UNITY verification system. In P. D. Mosses, M. Nielsen, and M. I. Schwartzbach, editors, TAPSOFT'95: Theory and Practice of Software Development: 6th International Conference: Proceedings, volume 915 of Lecture Notes in Computer Science, pages 795-796. Springer-Verlag, 1995.
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[20] F. Andersen and K. D. Petersen. Recursive boolean functions in HOL. In M. Archer, J. J. Joyce, K. N. Levitt, and P. J. Windley, editors, Proceedings of the 1991 International Workshop on the HOL Theorem Proving System and its Applications, Davis, August 1991, pages 367-377. IEEE Computer Society Press, 1992.
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[21] F. Andersen, K. D. Petersen, and J. S. Pettersson. A graphical tool for proving UNITY progress. In T. F. Melham and J. Camilleri, editors, Higher Order Logic Theorem Proving and Its Applications: 7th International Workshop, Valletta, Malta, September 1994: Proceedings, volume 859 of Lecture Notes in Computer Science, pages 17-32. Springer-Verlag, 1994.
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[22] F. Andersen, K. D. Petersen, and J. S. Pettersson. Program verification using HOL-UNITY. In J. J. Joyce and C.-J. H. Seger, editors, Higher Order Logic Theorem Proving and its Applications: 6th International Workshop, HUG'93, Vancouver, B.C., August 11-13 1993: Proceedings, volume 780 of Lecture Notes in Computer Science, pages 1-15. Springer-Verlag, 1994.
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[23] C. M. Angelo. Formal Hardware Verification in a Silicon Compilation Environment by means of Theorem Proving. PhD thesis, Katholieke Universiteit Leuven, February, 1994.
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[24] C. M. Angelo, L. Claesen, and H. De Man. Degrees of formality in shallow embedding hardware description languages in HOL. In J. J. Joyce and C.-J. H. Seger, editors, Higher Order Logic Theorem Proving and its Applications: 6th International Workshop, HUG'93, Vancouver, B.C., August 11-13 1993: Proceedings, volume 780 of Lecture Notes in Computer Science, pages 89-100. Springer-Verlag, 1994.
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[25] C. M. Angelo, L. Claesen, and H. De Man. The formal semantics definition of a multi-rate DSP specification language in HOL. In L. J. M. Claesen and M. J. C. Gordon, editors, Higher Order Logic Theorem Proving and its Applications: Proceedings of the IFIP TC10/WG10.2 International Workshop, Leuven, September 1992, IFIP Transactions A-20, pages 375-394. North-Holland, 1993.
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[26] C. M. Angelo, L. Claesen, and H. De Man. A methodology for proving correctness of parameterized hardware modules in HOL. In D. Borrione and R. Waxman, editors, Tenth International Symposium on Computer Hardware Description Languages and their Applications, CHDL'91: Marseille, France, pages 63-82. North-Holland, 1991.
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[27] C. M. Angelo, L. Claesen, and H. De Man. Modeling multi-rate DSP specification semantics for formal transformational design in HOL. Formal Methods in System Design, 5(1/2):61-94, July 1994.
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[28] C. M. Angelo, L. Claesen, and H. De Man. Reasoning about a class of linear systems of equations in HOL. In T. F. Melham and J. Camilleri, editors, Higher Order Logic Theorem Proving and Its Applications: 7th International Workshop, Valletta, Malta, September 1994: Proceedings, volume 859 of Lecture Notes in Computer Science, pages 33-48. Springer-Verlag, 1994.
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[29] C. M. Angelo, D. Verkest, L. Claesen, and H. De Man. On the comparison of HOL and Boyer-Moore for formal hardware verification. Formal Methods in System Design, 2(1):45-72, February 1993.
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[30] C. M. Angelo, D. Verkest, L. Claesen, and H. De Man. Formal hardware verification in HOL and in boyer-moore: A comparative analysis. In M. Archer, J. J. Joyce, K. N. Levitt, and P. J. Windley, editors, Proceedings of the 1991 International Workshop on the HOL Theorem Proving System and its Applications, Davis, August 1991, pages 340-347. IEEE Computer Society Press, 1992.
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[31] C. M. Angelo, D. Verkest, L. Claesen, and H. De Man. A synopsis on the comparison of HOL and Boyer-Moore for formal hardware verification. In P. Prinetto and P. Camurati, editors, Advanced Research Workshop on Correct Hardware Design Methodologies, pages 421-426. North-Holland, 1991.
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[32] M. Archer, G. Fink, and L. Yang. Linking other theorem provers to HOL using PM: Proof manager. In L. J. M. Claesen and M. J. C. Gordon, editors, Higher Order Logic Theorem Proving and its Applications: Proceedings of the IFIP TC10/WG10.2 International Workshop, Leuven, September 1992, IFIP Transactions A-20, pages 539-548. North-Holland, 1993.
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[33] M. Archer, J. J. Joyce, K. N. Levitt, and P. J. Windley, editors. Proceedings of the 1991 International Workshop on the HOL Theorem Proving System and its Applications, Davis, August 1991. IEEE Computer Society Press, 1992.
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[34] R. D. Arthan. A report on ICL HOL. In M. Archer, J. J. Joyce, K. N. Levitt, and P. J. Windley, editors, Proceedings of the 1991 International Workshop on HOL Theorem Proving System and its Applications, Davis, August 1991, pages 280-283. IEEE Computer Society Press, 1992.
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[35] R. D. Arthan. A formal specification of HOL. Technical Report DS/FMU/IED/SPC001, ICL Defence Systems, April 1990.
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[36] R. J. R. Back and J. von Wright. Predicate transformers and higher order logic. In J. W. de Bakker, W.-P. de Roever, and G. Rozenberg, editors, Semantics: Foundations and Applications: REX Workshop, Beekbergen, June 1992, volume 666 of Lecture Notes in Computer Science, pages 1-20. Springer-Verlag, 1993.
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[37] R. J. R. Back and J. von Wright. Refinement concepts formalised in higher order logic. Formal Aspects of Computing, 2(3):247-272, July-September 1990.
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[38] S. Bainbridge, A. Camilleri, and R. Fleming. Industrial application of theorem proving to system level design. In M. Archer, J. J. Joyce, K. N. Levitt, and P. J. Windley, editors, Proceedings of the 1991 International Workshop on the HOL Theorem Proving System and its Applications, Davis, August 1991, pages 130-142. IEEE Computer Society Press, 1992.
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[39] S. Bainbridge, A. Camilleri, and R. Fleming. Theorem proving as an industrial tool for system level design. In V. Stavridou, T. F. Melham, and R. T. Boute, editors, Theorem Provers in Circuit Design: Proceedings of the IFIP TC10/WG 10.2 International Conference, Nijmegen, June 1992, IFIP Transactions A-10, pages 253-274. North-Holland, 1992.
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[40] E. de Barros Lucena. Reasoning about petri nets in HOL. In M. Archer, J. J. Joyce, K. N. Levitt, and P. J. Windley, editors, Proceedings of the 1991 International Workshop on the HOL Theorem Proving System and its Applications, Davis, August 1991, pages 384-394. IEEE Computer Society Press, 1992.
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[41] R. H. Beers and P. J. Windley. Abstracting signals: The waveform library. In J. von Wright, J. Grundy, and J. Harrison, editors, Supplementary Proceedings of the 9th International Conference on Theorem Proving in Higher Order Logics: TPHOLs'96, number 1 in TUCS General Publication, pages 1-13. Turku Centre for Computer Science, August 1996.
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[42] G. Birtwistle and B. Graham. Verifying SECD in HOL. In J. Staunstrup, editor, Formal Methods for VLSI Design: IFIP WG10.2, Lecture Notes, pages 129-177. North-Holland, 1990.
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[43] G. Birtwistle, B. Graham, and S.-K. Chin. An introduction to hardware verification in higher order logic. Published electronically, August 1994.
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[44] G. Birtwistle, B. Graham, T. Simpson, K. Slind, M. Williams, and S. Williams. Verifying an SECD chip in HOL. In Proceedings of the IFIP WG 10.2/WG 10.5 International Workshop on Applied Formal Methods for Correct VLSI Design, pages 369-378. North Holland, 1990.
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[45] G. Birtwistle, B. Graham, T. Simpson, K. Slind, M. Williams, and S. Williams. Verifying an SECD chip in HOL. In L. J. M. Claesen, editor, Formal VLSI Correctness Verification: VLSI Design Methods-II: Proceedings of the IFIP WG 10.2/WG1 0.5 International Workshop on Applied Formal Methods for VLSI Design, Belgium, November 1989, pages 369-378. North-Holland, 1990.
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[46] G. Birtwistle, M. Hermann, T. Simpson, and K. Slind. From formal proof to netlist. In Proceedings of the Canadian Conference on VLSI, pages 217-224, Vancouver, British Columbia, Canada, 1989.
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[47] P. E. Black and P. J. Windley. Automatically synthesized term denotation predicates: A proof aid. In E. T. Schubert, P. J. Windley, and J. Alves-Foss, editors, Higher Order Logic Theorem Proving and Its Applications: 8th International Workshop, Aspen Grove, Utah, September 1995: Proceedings, volume 971 of Lecture Notes in Computer Science, pages 46-57. Springer-Verlag, 1995.
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[48] P. E. Black and P. J. Windley. Formal verification of secure programs in the presence of side effects. In Jr. R. H. Sprague, editor, Proceedings of the Thirty-first Hawai'i International Conference on System Sciences (HICSS-31), volume III, pages 327-334. IEEE Computer Science Press, 1998.
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[49] P. E. Black and P. J. Windley. Inference rules for programming languages with side effects in expressions. In J. von Wright, J. Grundy, and J. Harrison, editors, Theorem Proving in Higher Order Logics: 9th International Conference, Turku, Finland, August 1996: Proceedings, volume 1125 of Lecture Notes in Computer Science, pages 51-60. Springer-Verlag, 1996.
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[50] P. E. Black and P. J. Windley. Verifying resilient software. In Jr. R. H. Sprague, editor, Proceedings of the Thirty-first Hawai'i International Conference on System Sciences (HICSS-31), volume III, pages 262-266. IEEE Computer Science Press, 1998.
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[51] K. Blackburn. A report on ICL HOL. In D. Kapur, editor, Automated Deduction - CADE-11: 11th International Conference, Proceedings, volume 607 of Lecture Notes in Artificial Intelligence, pages 743-747. Springer-Verlag, 1992.
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[52] J.-P. Bodeviex and M. Filali. On the refinement of symmetric memory protocols. In E. T. Schubert, P. J. Windley, and J. Alves-Foss, editors, Higher Order Logic Theorem Proving and Its Applications: 8th International Workshop, Aspen Grove, Utah, September 1995: Proceedings, volume 971 of Lecture Notes in Computer Science, pages 58-74. Springer-Verlag, 1995.
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[53] J-P. Bodeviex, M. Filali, and P. Roche. Towards a HOL theory of memory. In T. F. Melham and J. Camilleri, editors, Higher Order Logic Theorem Proving and Its Applications: 7th International Workshop, Valletta, Malta, September 1994: Proceedings, volume 859 of Lecture Notes in Computer Science, pages 49-64. Springer-Verlag, 1994.
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[54] R. Boulton. Boyer-Moore automation for the HOL system. In L. J. M. Claesen and M. J. C. Gordon, editors, Higher Order Logic Theorem Proving and its Applications: Proceedings of the IFIP TC10/WG10.2 International Workshop, Leuven, September 1992, IFIP Transactions A-20, pages 133-142. North-Holland, 1993.
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[55] R. Boulton. Combining decision procedures in the HOL system. In E. T. Schubert, P. J. Windley, and J. Alves-Foss, editors, Higher Order Logic Theorem Proving and Its Applications: 8th International Workshop, Aspen Grove, Utah, September 1995: Proceedings, volume 971 of Lecture Notes in Computer Science, pages 75-89. Springer-Verlag, 1995.
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[56] R. J. Boulton. Efficiency in a fully-expansive theorem prover. Technical Report 337, University of Cambridge Computer Laboratory, May 1994.
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[57] R. Boulton. A lazy approach to full-expansive theorem proving. In L. J. M. Claesen and M. J. C. Gordon, editors, Higher Order Logic Theorem Proving and its Applications: Proceedings of the IFIP TC10/WG10.2 International Workshop, Leuven, September 1992, IFIP Transactions A-20, pages 19-38. North-Holland, 1993.
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[58] R. J. Boulton. Lazy techniques for fully expansive theorem proving. Formal Methods in System Design, 3(1-2):25-47, August 1993.
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[59] R. J. Boulton. On efficiency in theorem provers which fully expand proofs into primitive inferences. Technical Report 248, University of Cambridge Computer Laboratory, February 1992.
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[60] R. Boulton. A restricted form of higher-order rewriting applied to an HDL semantics. In J. Hsiang, editor, Rewriting Techniques and Applications: 6th International Conference: Proceedings, volume 914 of Lecture Notes in Computer Science, pages 309-323. Springer-Verlag, 1995.
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[61] R. Boulton, A. Gordon, M. Gordon, J. Harrison, J. Herbert, and J. Van Tassel. Experience with embedding hardware description languages in HOL. In V. Stavridou, T. F. Melham, and R. T. Boute, editors, Theorem Provers in Circuit Design: Proceedings of the IFIP TC10/WG 10.2 International Conference, Nijmegen, June 1992, IFIP Transactions A-10, pages 129-156. North-Holland, 1992.
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[62] R. Boulton, M. Gordon, J. Herbert, and J. Van Tassel. The HOL verification of ELLA designs. Appeared in the Unpublished Proceedings of the International Workshop on Formal Methods in VLSI Design, Miami, Florida January 1991, 1991.
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[63] R. Boulton and K. Slind. Automatic derivation and application of induction schemes for mutually recursive functions. In J. Lloyd, V. Dahl, U. Furbach, M. Kerber, K.-K. Lau, C. Palamidessi, L. Moniz Pereira, Y. Sagiv, and P. J. Stuckey, editors, Computational Logic: First International Conference, CL2000, London, UK, July 2000: Proceedings, volume 1861, pages 629-643. Springer-Verlag, 2000.
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[64] R. Boulton, K. Slind, A. Bundy, and M. Gordon. An interface between Clam and HOL. In J. Grundy and M. Newey, editors, Theorem Proving in Higher Order Logics, 11th International Conference, TPHOLs'98, Canberra: Proceedings, volume 1479 of Lecture Notes in Computer Science, pages 87-104. Springer-Verlag, 1998.
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[65] J. Bowen, editor. Towards Verified Systems, volume 2 of Real-Time Safety Critical Systems Series. Elsevier, 1994.
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[66] J. P. Bowen and M. J. C. Gordon. A shallow embedding of Z in HOL. Information and Software Technology, 37(5-6):269-276, May/June 1995.
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[67] J. P. Bowen and M. J. C. Gordon. Z and HOL. In J. P. Bowen and J. A. Hall, editors, Z User Workshop, Cambridge 1994, Workshops in Computing Series, pages 141-167. Springer-Verlag, 1994.
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[68] S. H. Brackin. Deciding cryptographic protocol adequacy with HOL. In E. T. Schubert, P. J. Windley, and J. Alves-Foss, editors, Higher Order Logic Theorem Proving and Its Applications: 8th International Workshop, Aspen Grove, Utah, September 1995: Proceedings, volume 971 of Lecture Notes in Computer Science, pages 90-105. Springer-Verlag, 1995.
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[69] S. H. Brackin. Deciding cryptographic protocol adequacy with HOL: The implementation. In J. von Wright, J. Grundy, and J. Harrison, editors, Theorem Proving in Higher Order Logics: 9th International Conference, Turku, Finland, August 1996: Proceedings, volume 1125 of Lecture Notes in Computer Science, pages 61-76. Springer-Verlag, 1996.
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[70] S. H. Brackin. Providing tractable security analyses in HOL. In T. F. Melham and J. Camilleri, editors, Higher Order Logic Theorem Proving and Its Applications: 7th International Workshop, Valletta, Malta, September 1994: Proceedings, volume 859 of Lecture Notes in Computer Science, pages 65-80. Springer-Verlag, 1994.
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[71] S. H. Brackin and S.-K. Chin. Server-process restrictiveness in HOL. In J. J. Joyce and C.-J. H. Seger, editors, Higher Order Logic Theorem Proving and its Applications: 6th International Workshop, HUG'93, Vancouver, B.C., August 11-13 1993: Proceedings, volume 780 of Lecture Notes in Computer Science, pages 450-463. Springer-Verlag, 1994.
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[72] Michael Butler, Jim Grundy, Thomas Långbacka, Rimvydas Ruksenas, and Joakim von Wright. The refinement calculator: Proof support for program refinement. In Lindsay Groves and Steve Reeves, editors, Formal Methods Pacific'97: Proceedings of FMP'97, Discrete Mathematics & Theoretical Computer Science, pages 40-61, Wellington, New Zealand, July 1997. Springer-Verlag.
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[83] J. Camilleri and V. Zammit. Symbolic animation as a proof tool. In T. F. Melham and J. Camilleri, editors, Higher Order Logic Theorem Proving and Its Applications: 7th International Workshop, Valletta, Malta, September 1994: Proceedings, volume 859 of Lecture Notes in Computer Science, pages 113-127. Springer-Verlag, 1994.
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[90] V. A. Carreño. Definition and partial verification of data routing circuit in hol. July 1991.
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[91] V. A. Carreño. Transition Assertions: A Higher-Order Logic Based Method for the Specification and Verfication of Real-Time Systems. PhD thesis, University of Cambridge Computer Laboratory, 1997.
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[92] V. A. Carreño. The transition assertions specification method. Technical Report 279, Computer Laboratory, University of Cambridge, January 1993.
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[93] V. A. Carreño. Verification in higher order logic of mutual exclusion algorithm. In J. J. Joyce and C.-J. H. Seger, editors, Higher Order Logic Theorem Proving and its Applications: 6th International Workshop, HUG'93, Vancouver, B.C., August 11-13 1993: Proceedings, volume 780 of Lecture Notes in Computer Science, pages 501-513. Springer-Verlag, 1994.
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[94] V. A. Carre o and P. S. Miner. Specification of the IEEE-854 floating-point standard in HOL and PVS. In J. Alves-Foss, editor, HOL-95: International Workshop on Higher Order Logic Theorem Proving and its Applications: B-Track: Short Presentations, Aspen Grove, Utah, September, 1995, pages 1-16, 1995.
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[95] S.-K. Chin. Combining engineering vigor with mathematical rigor. In M. Leeser and G. Brown, editors, Hardware Specification, Verification and Synthesis: Mathematical Aspects: Mathematical Sciences Institute Workshop, Cornell, July 1989, volume 408 of Lecture Notes in Computer Science, pages 152-176. Springer-Verlag, 1990.
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[96] S.-K. Chin. Verified functions for generating signed-binary arithmetic hardware. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11(12):1529-1558, December 1992.
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[97] S.-K. Chin. Verified synthesis functions for negabinary arithmetic hardware. In L. J. M. Claesen, editor, Formal VLSI Correctness Verification: VLSI Design Methods-II: Proceedings of the IFIP WG 10.2/WG1 0.5 International Workshop on Applied Formal Methods for VLSI Design, Belgium, November 1989, pages 187-196. North-Holland, 1990.
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